1. Field of the Invention
The present invention relates to a stacked memory having a plurality of stacked semiconductor chips, and particularly to a stacked memory having error checking and correcting (ECC) bits.
2. Description of the Related Art
Recently, configuration of semiconductor devices has been refined, and the capacity of semiconductor memories such as dynamic random access memories (DRAMs) and static random access memories (SRAMs) has been increased. On the other hand, the size of electronic equipment on which these semiconductor memories are mounted has been reduced. Therefore, the semiconductor memories have evolved as three-dimensional stacked memories having a plurality of stacked semiconductor chips while increasing the capacity thereof. The three-dimensional stacked memory has a plurality of stacked semiconductor chips, which are wire-bonded and packaged in a single package. Thus, the size of a large-capacity semiconductor device is reduced by stacking semiconductor chips to form a three-dimensional stacked memory.
Further, more recent development has led to a stacked memory using a through electrode instead of wire bonding for the purpose of realizing a semiconductor device with a further reduced size and increased operation speed. In such a stacked memory, stacked semiconductor chips are connected to each other by a through electrode formed through the semiconductor chips. It is expected that the usage of the through electrode reduces the space and inductance due to the wire bonding, and is able to achieve a semiconductor device having a further reduced size and a higher operating speed. The stacked memory can be configured as a memory module or memory system by stacking a plurality of memory chips. This stacked memory can be exemplified by a stacked DRAM having stacked DRAM chips.
A large-capacity memory system is configured to include an error checking and correcting bit (hereafter, referred to as the “ECC bit”). Any error is detected and corrected by this ECC bit to ensure data reliability. In a conventional memory module having an ECC bit, a monolithic memory is arranged planarly on a memory module substrate, and an additional data bus for the ECC bit is provided separately from a data bus. Therefore, the ratio between data bits and ECC bits can be changed easily by adding data buses as required.
In contrast, in the case of a stacked memory, a data bus is used commonly by a data bit and an ECC bit because memory chips are arranged three-dimensionally. In a three-dimensional configuration, the positions of through electrodes are common to all the memory chips. Therefore, a separate data bus cannot be provided for an ECC bit. If a separate data bus is provided for an ECC bit in a three-dimensional configuration, part of memory capacity will be wasted, impairing the effective use of the memory capacity. Accordingly, it becomes difficult for the stacked memory to change the ratio between data bits and ECC bits.
FIG. 1 is a configuration diagram showing a memory module having an ECC bit according to a related art in which a monolithic memory is arranged planarly, and FIG. 2 is a configuration diagram showing a stacked memory using a through electrode.
FIG. 1A shows a case in which the ratio between data bits and ECC bits is 8:1. A memory module 10 is comprised of nine semiconductor memories 1 in total: eight for data bits and one for an ECC. In this example, an eight-bit semiconductor memory is used as each semiconductor memory 1. The memory module is provided with 72-bit bus wiring in total, namely 64-bit (8 by 8) bus wiring for the data bits and eight-bit bus wiring for the ECC bit.
FIG. 1B shows a case in which the ratio between data bits and ECC bit is 4:1. The memory module 10 is comprised often semiconductor memories 1 in total: eight for data bits and two for ECC bits. Each semiconductor memory 1 is formed by an eight-bit memory. The memory module is provided with 80-bit bus wiring in total, namely 64-bit (8 by 8) bus wiring for the data bits and 16-bit bus wiring for the ECC bits. In an existing memory module, a plurality of semiconductor memories are arranged, and a data wiring is provided for each of the semiconductor memories. A same address is input to the semiconductor memories, and data is input/output through each data wiring. A memory module having an ECC bit can be obtained by adding data wiring to a memory module substrate.
This memory module is configured as a stacked memory having stacked memory chips with through electrodes. When the ratio between data bits and ECC bits is 8:1 (FIG. 2A), the memory module is comprised of nine layers of memory chips 2 in total consisting of eight data layers 3 and one ECC layer 4. When the ratio between data bits and ECC bits is 4:1 (FIG. 2B), the memory module is comprised of ten layers of memory chips 2 in total consisting of eight data layers 3 and two ECC layers 4. In the stacked memory, the positions of the through electrodes are common to all the memory chips. Therefore, a memory bus for data and a memory bus for ECC bit are used in common. It is impossible to add a data bus as in the prior art. If an additional data bus is assigned for an ECC bit, a part of the memory capacity will be lost, impairing the effective use of the memory capacity. Consequently, there is a problem that it is difficult to configure a stacked memory having ECC bits or to change the ratio between data bits and ECC bits.
Stacked semiconductor devices having stacked semiconductor chips are described in patent documents as follows. Japanese Laid-Open Patent Publication No. 2006-13337 (Patent Document 1) relates to a technique in which one of a plurality of inter-chip wirings serving as signal transmission paths of a stacked semiconductor device is selected, while the other wirings are electrically disconnected. Japanese Laid-Open Patent Publication No. 2006-12358 (Patent Document 2) discloses a technique in which a memory cell array is provided with sub-banks corresponding to input/output bits, and inter-chip wirings are provided through memory chips so that the quantity of input bits is equal to that of output bits. Japanese Laid-Open Patent Publication No. 2006-12337 (Patent Document 3) discloses an interface chip having a bit configuration switching circuit for changing input and output bit configurations of memory chips.
Japanese Laid-Open Patent Publication No. 2004-327474 (Patent Document 4) relates to a technique in which a plurality of memory chips are stacked on an IO chip and connected by ways of through electrodes, and a system data signal and a data signal from the memory chip are converted by the IO chip. Japanese Laid-Open Patent Publication No. 2003-163326 (Patent Document 5) relates to a technique in which select wirings are provided for connecting a chip select signal terminal to chip select terminals of a plurality of semiconductor chips, and one of the semiconductor chips is selected by cutting the select wirings. Japanese Kohyo Patent Publication No. 2002-516033 (Patent Document 6) discloses a plurality of memory circuits and a single control circuit which are joined at a vertical junction. The patent documents mentioned above disclose a stacked semiconductor device having a switching circuit or fuse for switching signals. However, none of the patent documents recognizes the problems to be solved by the present invention, or implies or suggests a technique to solve the problems.